2: BPD schemes afford different scaling benefits associated with increasing levels of wafer processing complexity. The second is thinning the backside silicon to deliver as direct and as low resistance a connection as possible in a repeatable and controllable manner,” said Natarajan.īecause BPD approaches are so new, the industry is weighing the pros and cons to different architectures.įig. Nonetheless, a backside power network introduces substantial wafer processing challenges - especially since the change can occur at the same node as the device maker’s switch from finFETs to nanosheet transistors.įor instance, Intel will introduce RibbonFET and PowerVia at its 20A (2nm) node “The first key challenge around PowerVia involves patterning an electrical contact feature within the tight spaces around next-generation RibbonFET transistors without impacting their performance. It also allows these different metal layers to be optimally fabricated - as wider lines for Vdd and Vss, and thinner lines to carry signals. 1: Interconnect levels on traditional logic device (left) and backside power distribution network with PowerVia (right). “Intel then has the option to be less aggressive on interconnect scaling without skipping a beat on transistor density scaling. This allows for less complex and ultimately less expensive lower layer metal patterning.”įig. “Backside power delivery removes the need for a power delivery track from lower layer front-side interconnects,” said Sanjay Natarajan, senior vice president and co-general manager for Logic Technology Development at Intel. In addition to relieving the RC bottleneck, BPD enables cost savings. Intel, Samsung and TSMC all have announced plans to implement BPD in some form at around the 2nm node. Instead, as the name implies, power is moved to the back of the wafer so only signals are carried by frontside interconnects. This novel approach enhances signal integrity and reduces routing congestion, but it also creates some new challenges for which today there are no simple solutions.īackside power delivery (BPD) eliminates the need to share interconnect resources between signal and power lines on the wafer frontside. One of the key technologies to enable scaling below 3nm involves delivering of power on the backside of a chip.
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